64 x 1 MULTIPLEXER using 8 x 1 multiplexer (Structural) Mod 10 Up Counter ( Verilog ) with Test fixture; Full Subtractor ( Verilog ) with Test Fixture; Mod 5 Up Counter (Verilog) with Test Fixture; EVEN / ODD COUNTER (Behavioral) FULL ADDER using Two HALF ADDERS and One Or gate (STRUCTURAL) 3-Bit UP / DOWN Counter ( Structural ) with Test Bench.
Active4 years, 3 months ago
i need a frequency divider in verilog, and i made the code below. It works, but i want to know if is the best solution, thanks!
the circuit generated by quartus:
Guilherme StéfanoGuilherme Stéfano
1 Answer
Your block divides the frequency by 4 not 2. There is actually quite a good description of this on Wikipedia Digital Dividers. Your code can be tidied up a bit but only 1 D-Type is required, which is smaller than a JK Flip-flop so is optimal.
When chaining these types of clock dividers together be aware that there is a clk to q latency which is compounded every time you go through one of these dividers. IF this is not managed correctly by synthesis the clocks can not be considered synchronous.
Example on EDAplayground, should open the waveform when run.
Not the answer you're looking for? Browse other questions tagged verilogclockfrequencycircuitdigital-logic or ask your own question.
(Image originally created by Digilent Inc.; modified by me for this this tutorial) The previous module introduced, and hopefully drove home, the concept of instantiation in Verilog. Now we will take a look at a couple advanced topics (second topic to be added soon) regarding module instantiation. Counter controlled instantiation: What if we needed to generate a bunch (take 50 as an example) of DFFs that were all connected together in a clock divider circuit... We already know how to make a general DFF module, so now we need to instantiate it 50 times and connect the clock pin of each one to the output of the DFF that is sequentially before it, connect reset to a global reset, and the D in pin to the inverse of the DFF's output (Q). Use the attached diagram for reference. This would be a lot of instantiations for you to write (50 instantiations times 6 lines per instantiation is 300 lines!) by hand. But in Verilog we can use a counter controller loop, specifically, a 'for' loop, to instantiate (generate) all of these modules (except for the first one) for us in very few lines of code. But there is one caveat; we have to carefully plan our design so that we can use a 'generate loop' properly. Note that the way we connect each DFF to the next is uniform and predictable. Of course, the first DFF's clock will be the clock input from our top level module, and the output of the last DFF will go somewhere in the top level module, but we can deal with those individually; during the generation, each internal wire in the design except for the first clock that we will manually designate and the last output wire will be explicitly given a source and a drain. The software knows that the two remaining wires need either a source (first clock) or drain (last data) and it is the engineer's responsibility to provide one. As mentioned before, you have to set up the design properly in order to use a generate loop. What does this involve? Well, it makes sense that since each DFF is going to have a clock in dependent on the previous one (not including the first one!) that we can group together these similar signals in a bus! This lets us refer to signal groups like an array in C/C++ and call individual wires by index using the [] operator.
The reset pin for each DFF will come from a common reset, since each DFF needs to be able to reset at the same time. Without knowing the specifics of a generate loop yet, we can still make our bus that will be used in the design. What type of bus will we make? Since these are only carrying a signal from a source to a drain, we will make wires. wire out[49:0] //50 bit wide bus for DFF output/input We can also instantiate our first DFF. Using the DFF module from Tutorial Module 3.2, and assuming our clock divider has an input clk (a clock pin), an input rst (a reset pin), and an output out (let's say it will drive an LED, creating a blinking effect). dff dff0( .clk(clk), .rst(rst), .D(~out[0]), .Q(out[0]) ); Now, the generate loop. It is similar to a loop in C/C++ but has its own nuances. First we need to create a counter variable. In Verilog the variable type is called 'genvar' and it is used to declare a variable, call it 'y', like so: genvar y; The generate loop begins with the keyword 'generate' and ends with 'endgenerate'. Note: You must declare any genvar variables outside the scope of the generate loop. We now have: genvar y; generate endgenerate Immediately following the 'generate' keyword is the actual loop. Its declaration is like a loop in C/C++, but in Verilog, we don't have the luxury of left and right curly braces ( { and } ) but we do have the Verilog equivalent: begin and end. Additionally, Verilog does not support postfix operations, so we can't state 'y++' and must instead state 'y = y + 1'. When constructing the for loop, keep in mind that we already created the first DFF (DFF0) so we will generate from 1 to 49 (smaller than 50). genvar y; generate for(y = 1; y < 50; y = y + 1 ) //spaces may be omitted begin end endgenerate With a generate loop, we are going to 'begin' an instantiation loop and must give this process a name. We will not use this name for any other purpose and will not refer to it later in our design (it is used internally in the synthesizer). We do this by adding a statement following the format ' : ' and place it on the same line as the 'begin' for good style. Let's call this 'dff_generation': genvar y; generate for(y = 1; y < 50; y = y + 1 ) //spaces may be omitted begin : dff_generation end endgenerate Now is the crucial and most difficult part: creating the instantiation model. This will look just like any other instantiation except that the wires you pass the module are allowed to use the genvar as a value or value modifier. Recall that the genvar's value will change by one in this case after each instantiation. Rather than walk through each line of the instantiation I'll give you the entire block of code and point out things you may not recognize. Be sure to refer to the provided picture to see how this circuit is implemented. genvar y; generate for(y = 1; y < 50; y = y + 1 ) //spaces may be omitted begin : dff_generation //the below instance name doesn't matter dff dff_insts ( .clk(out[y-1]), //clk in of DFF 'y' is out of 'y-1' .rst(rst), //each DFF gets the same reset .D(~out[y]), //input is fed the inverted output .Q(out[y]) //output ); end endgenerate I encourage you to hand trace a few iterations of the loop to see how the generation process works. The synthesizer will give each instance it creates a unique indexed name such as 'dff_insts1' and 'dff_insts2'.